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Master Thesis / Working Student Mixed-Signal Modelling and Design Verification

STMicroelectronicsvor 4 TagenWerkstudent
Vor OrtEnglisch erforderlichIngenieurwesenHardware-Entwicklung

Erforderliche Skills

Analog circuitsEDA toolsSystemVerilogVirtuoso SKILLMixed-Signal verificationPythonCadenceVerilog

Stellenbeschreibung

STMicroelectronics hat diese Anzeige veröffentlicht. Wir haben unten unseren eigenen Werkstudenten-Kontext ergänzt — was diese Stelle für deine Wochenstunden, dein Netto und dein Studierendenvisum als Studierende:r in Munich, Deutschland bedeutet.

Beschreibung bereitgestellt von STMicroelectronics

OUR STORY

At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.

When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.

Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.

Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.

YOUR ROLE

You take part in creating the best new hire experience in the project to completely renew our talent acquisition and onboarding process. You also help us with finding the best vendors for recruitment, and managing the a to z collaboration with them.

  • We are looking for a motivated student to join our Power Management IC Design Verification Team. In this role, you will actively contribute to IC top-level verification tasks and flow development. Your work will focus on enhancing verification flows in line with the latest advancements in Mixed-Signal top-level verification and analog behavioral model development. These improvements will adhere to IEEE/Accellera standards and leverage the reference manuals of leading Electrical Design Automation (EDA) tools and flows.
  • You will also collaborate closely with EDA vendors such as Cadence, Synopsys, and Mentor, gaining hands-on experience in cutting-edge verification methodologies.
  • This position offers a unique opportunity to explore, understand, and implement innovative verification concepts in a productive and impact way.

Your Skills & Experiences

  • Degree in Electronics or similar course of studies.
  • Basic understanding of analog circuits and simulators.
  • Familiarity with Cadence design flows.
  • Understanding Hardware description languages (Verilog, SystemVerilog).
  • Strong programming skills, particularly in Python.
  • Knowledge of Virtuoso SKILL language is a plus.
  • A willingness to learn, understand, and apply new concepts.

ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.

At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.

To discover more, visit st.com/careers.

Wichtiges für Werkstudierende

Was diese Werkstudentenstelle im Bereich Ingenieurwesen in Munich für dich bedeutet — die Wochenstundenregeln, Vorteile bei den Sozialabgaben und worauf internationale Studierende vor der Bewerbung achten sollten.

Wochenstunden

Werkstudierende dürfen während des Semesters bis zu 20 Stunden pro Woche arbeiten, in den Semesterferien Vollzeit. Wer das einhält, behält den Studierendenstatus und die Werkstudentenvorteile.

Werkstudenten-Regeln

Sozialabgaben

Dank des Werkstudentenprivilegs zahlst du keine Beiträge zur Kranken-, Pflege- und Arbeitslosenversicherung — nur die Rentenversicherung greift. Dir bleibt mehr netto als in einem regulären Job.

Versicherung prüfen

Internationale Studierende

Studierende von außerhalb der EU dürfen 140 volle oder 280 halbe Tage im Jahr arbeiten (seit März 2024, zuvor 120/240). Ein Werkstudentenvertrag passt meist in diesen Rahmen — prüfe die genauen Grenzen auf deinem Aufenthaltstitel.

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